magzatelhajtás Joseph Banks Hatékony single event latchup általánosít Széleskörű Fénykép
PDF] Single event latchup: Hardening strategies, triggering mechanisms, and testing considerations | Semantic Scholar
Single event and TREE latchup mitigation for a star tracker sensor: An innovative approach to system level latchup mitigation - UNT Digital Library
SEECA - Section 4
Latch-up - Wikipedia
Single Event Latchup over-current seen for half A of Daughterboard 5... | Download Scientific Diagram
SINGLE EVENT LATCHUP: HARDENING STRATEGIES, TRIGGERING MECHANISMS, AND TESTING CONSIDERATIONS
ESD testing: Latchup
Single Event Effects (SEEs) with High Speed ADCs: Single Event Latch-up (SEL) - Planet Analog
Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch | SpringerLink
Comparative research on “high currents” induced by single event latch-up and transient-induced latch-up<xref ref-type="fn" rid="cpb142021fn1">*</xref>
Figure 1 from Preventing single event latchup with deep P-well on P-substrate | Semantic Scholar
SEE Single Event Effects
Latch-up - Wikipedia
EngineerZone
Modeling and Analysis of Single Event Effects (SEE) - SemiWiki
A Single Event Latch-up protection method for SRAM FPGA | Semantic Scholar
What are random Destructive Single Event Effects (DSEE)? | TI.com Video
Single event latch-up (SEL) and single event upset (SEU) static random... | Download Scientific Diagram
SEE Single Event Effects Radiation Environment and its Effects in EEE Components and Hardness Assurance for Space Applications César Boatella Polo (TEC-QEC) - ppt download
Integrated Single Event Latchup protection for ASICs used in space applications | Semantic Scholar
5: Single Event Latch-up principle. | Download Scientific Diagram
Single-Event Latchup sensitivity: Temperature effects and the role of the collected charge - ScienceDirect
A tutorial in radiation-induced single event upsets - Embedded Computing Design
SEE Single Event Effects
Compact Modeling of Single Event Latchup of integrated CMOS circuit
Figure 1 from Single-Event Latchup Modeling Based on Coupled Physical and Electrical Transient Simulations in CMOS Technology | Semantic Scholar
5: Single Event Latch-up principle. | Download Scientific Diagram